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mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 1 - preliminary document title multi-chip package memory 32m bit (4mx8/2mx16) dual bank nor flash memory / 8m(1mx8/512kx16) full cmos sram the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserve the right to change the spec ifications and products. samsung electronics will answer to your questions about device. if you have any questions, please contact the samsung branch offices. revision history revision no. 0.0 remark preliminary history initial draft draft date november 6, 2002
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 2 - preliminary multi-chip package memory 32m bit (4mx8/2mx16) dual bank nor flash memory / 8m(1mx8/512kx16) full cmos sram the k5a3x80yt(b)c featuring single 3.0v power supply is a multi chip package memory which combines 32mbit dual bank flash and 8mbit fcmos sram. the 32mbit flash memory is organized as 4m x8 or 2m x16 bit and 8mbit sram is organized as 1m x8 or 512k x16 bit. the memory architecture of flash memory is designed to divide its memory arrays into 71 blocks and this provides highly flexible erase and program capability. this device is capable of reading data from one bank while programming or erasing in the other bank with dual bank organization. the flash memory performs a program operation in units of 8 bits (byte) or 16 bits (word) and erases in units of a block. single or multiple blocks can be erased. the block erase operation is com- pleted for typically 0.7sec. the 8mbit sram supports low data retention voltage for battery backup operation with low data retention current. the k5a3x80yt(b)c is suitable for the memory of mobile com- munication system to reduce mount area. this device is available in 69-ball tbga type package. features power supply voltage : 2.7v to 3.3v organization - flash : 4,194,304 x 8 / 2,097,152 x 16 bit - sram : 1,048,576 x 8 / 524,288 x 16 bit access time (@2.7v) - flash : 70 ns, sram : 55 ns power consumption (typical value) - flash read current : 14 ma (@5mhz) program/erase current : 15 ma standby mode/autosleep mode : 5 m a read while program or read while erase : 25 ma - sram operating current : 22 ma standby current : 0.5 m a secode(security code) block : extra 64kb block (flash) block group protection / unprotection (flash) flash bank size : 8mb / 24mb , 16mb / 16mb flash endurance : 100,000 program/erase cycles minimum sram data retention : 1.5 v (min.) industrial temperature : -40 c ~ 85 c package : 69-ball tbga type - 8 x 11mm, 0.8 mm pitch 1.2mm(max.) thickness general description samsung electronics co., ltd. reserves the right to change products and specifications without notice. ball configuration ball description ball name description a 0 to a 18 address input balls (common) a-1, a 19 to a 20 address input balls (flash memory) dq 0 to dq 15 data input/output balls (common) reset hardware reset (flash memory) wp /acc write protection / acceleration program (flash memory) vcc s power supply (sram) vcc f power supply (flash memory) vss ground (common) ub upper byte enable (sram) lb lower byte enable (sram) byte s byte s control (sram) byte f byte f control (flash memory) sa address inputs (sram) ce f chip enable (flash memory) cs 1 s chip enable (sram low active) cs2 s chip enable (sram high active) we write enable (common) oe output enable (common) ry/ by ready/busy (flash memory) n.c no connection top view (ball down) a 7 u b a 8 a 3 a 6 r e s e t l b c s 2 s a 1 9 a 2 a 5 a 1 8 r y / b y a 2 0 a 9 a 4 d q 6 c e f o e d q 9 d q 3 d q 4 d q 1 3 1 2 3 4 5 6 a b c d e f w p / w e v s s a 1 0 d q 1 a 0 a 1 a 1 7 a 1 1 a 1 2 a 1 5 a 1 3 n . c a 1 4 s a a 1 6 d q 1 5 b y t e f 7 8 n . c d q 8 d q 2 d q 1 1 d q 5 h d q 1 4 c s 1 s d q 0 d q 1 0 v c c f v c c s d q 1 2 g d q 7 v s s b y t e s / a - 1 n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c n . c 9 1 0 k j 69 ball tbga , 0.8mm pitch a c c
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 3 - preliminary ordering information k 5 a 3 x 8 0 y t c - t 7 5 5 samsung mcp memory device type dual bank boot block nor + fcmos sram nor flash density (bank size), (organization) 32 : 32mbit, (8mb, 24mb) (x8/x16 selectable) 33 : 32mbit, (16mb, 16mb) (x8/x16 selectable) block architecture t = top boot block b = bottom boot block version c = 4th generation sram access time 55 = 55 ns operating voltage range 2.7v to 3.3v package t = 69 tbga sram density , organization 8mbit, x8/x16 selectable bottom boot block figure 1. functional block diagram precharge circuit. i/o circuit column select clk gen. row select data control control logic sram (512k x16, 1m x8) main cell array a0 to a18 a-1,a 19 to a20 ce f oe ub cs 1 s dq 0 to dq 7 dq 8 to dq 15 vcc s vss we vcc f vss rd/ by i/o interface & bank control x dec y dec latch & control latch & control dec x y dec erase control program control high voltage gen. bank2 cell array bank1 address bank2 address bank1 data-in/out bank2 data-in/out bank1 cell array cs2 s lb (common) byte f byte s sa reset flash access time 7 = 70 ns 8 = 80 ns
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 4 - preliminary table 1. flash memory top boot block address (k5a3280yt/k5a3380yt) k5 a3280 yt k5 a3380 yt block block address block size (kb/kw) address range a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode bank1 bank1 ba70 1 1 1 1 1 1 1 1 1 8/4 3fe000h-3fffffh 1ff000h-1fffffh ba69 1 1 1 1 1 1 1 1 0 8/4 3fc000h-3fdfffh 1fe000h-1fefffh ba68 1 1 1 1 1 1 1 0 1 8/4 3fa000h-3fbfffh 1fd000h-1fdfffh ba67 1 1 1 1 1 1 1 0 0 8/4 3f8000h-3f9fffh 1fc000h-1fcfffh ba66 1 1 1 1 1 1 0 1 1 8/4 3f6000h-3f7fffh 1fb000h-1fbfffh ba65 1 1 1 1 1 1 0 1 0 8/4 3f4000h-3f5fffh 1fa000h-1fafffh ba64 1 1 1 1 1 1 0 0 1 8/4 3f2000h-3f3fffh 1f9000h-1f9fffh ba63 1 1 1 1 1 1 0 0 0 8/4 3f0000h-3f1fffh 1f8000h-1f8fffh ba62 1 1 1 1 1 0 x x x 64/32 3e0000h-3effffh 1f0000h-1f7fffh ba61 1 1 1 1 0 1 x x x 64/32 3d0000h-3dffffh 1e8000h-1effffh ba60 1 1 1 1 0 0 x x x 64/32 3c0000h-3cffffh 1e0000h-1e7fffh ba59 1 1 1 0 1 1 x x x 64/32 3b0000h-3bffffh 1d8000h-1dffffh ba58 1 1 1 0 1 0 x x x 64/32 3a0000h-3affffh 1d0000h-1d7fffh ba57 1 1 1 0 0 1 x x x 64/32 390000h-39ffffh 1c8000h-1cffffh ba56 1 1 1 0 0 0 x x x 64/32 380000h-38ffffh 1c0000h-1c7fffh ba55 1 1 0 1 1 1 x x x 64/32 370000h-37ffffh 1b8000h-1bffffh ba54 1 1 0 1 1 0 x x x 64/32 360000h-36ffffh 1b0000h-1b7fffh ba53 1 1 0 1 0 1 x x x 64/32 350000h-35ffffh 1a8000h-1affffh ba52 1 1 0 1 0 0 x x x 64/32 340000h-34ffffh 1a0000h-1a7fffh ba51 1 1 0 0 1 1 x x x 64/32 330000h-33ffffh 198000h-19ffffh ba50 1 1 0 0 1 0 x x x 64/32 320000h-32ffffh 190000h-197fffh ba49 1 1 0 0 0 1 x x x 64/32 310000h-31ffffh 188000h-18ffffh ba48 1 1 0 0 0 0 x x x 64/32 300000h-30ffffh 180000h-187fffh bank2 ba47 1 0 1 1 1 1 x x x 64/32 2f0000h-2fffffh 178000h-17ffffh ba46 1 0 1 1 1 0 x x x 64/32 2e0000h-2effffh 170000h-177fffh ba45 1 0 1 1 0 1 x x x 64/32 2d0000h-2dffffh 168000h-16ffffh ba44 1 0 1 1 0 0 x x x 64/32 2c0000h-2cffffh 160000h-167fffh ba43 1 0 1 0 1 1 x x x 64/32 2b0000h-2bffffh 158000h-15ffffh ba42 1 0 1 0 1 0 x x x 64/32 2a0000h-2affffh 150000h-157fffh ba41 1 0 1 0 0 1 x x x 64/32 290000h-29ffffh 148000h-14ffffh ba40 1 0 1 0 0 0 x x x 64/32 280000h-28ffffh 140000h-147fffh ba39 1 0 0 1 1 1 x x x 64/32 270000h-27ffffh 138000h-13ffffh ba38 1 0 0 1 1 0 x x x 64/32 260000h-26ffffh 130000h-137fffh ba37 1 0 0 1 0 1 x x x 64/32 250000h-25ffffh 128000h-12ffffh ba36 1 0 0 1 0 0 x x x 64/32 240000h-24ffffh 120000h-127fffh ba35 1 0 0 0 1 1 x x x 64/32 230000h-23ffffh 118000h-11ffffh
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 5 - preliminary table 1. flash memory top boot block address (k5a3280yt/k5a3380yt) note: the address range is a20 ~ a-1 in the byte mode ( byte f = v il ) or a20 ~ a0 in the word mode ( byte f = v ih ). the bank address bits is a20 ~ a19 for k5a3280yt, a20 for k5a3380yt. k5 a3280 yt k5 a3380 yt block block address block size (kb/kw) address range a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode bank2 bank1 ba34 1 0 0 0 1 0 x x x 64/32 220000h-22ffffh 110000h-117fffh ba33 1 0 0 0 0 1 x x x 64/32 210000h-21ffffh 108000h-10ffffh ba32 1 0 0 0 0 0 x x x 64/32 200000h-20ffffh 100000h-107fffh bank2 ba31 0 1 1 1 1 1 x x x 64/32 1f0000h-1fffffh 0f8000h-0fffffh ba30 0 1 1 1 1 0 x x x 64/32 1e0000h-1effffh 0f0000h-0f7fffh ba29 0 1 1 1 0 1 x x x 64/32 1d0000h-1dffffh 0e8000h-0effffh ba28 0 1 1 1 0 0 x x x 64/32 1c0000h-1cffffh 0e0000h-0e7fffh ba27 0 1 1 0 1 1 x x x 64/32 1b0000h-1bffffh 0d8000h-0dffffh ba26 0 1 1 0 1 0 x x x 64/32 1a0000h-1affffh 0d0000h-0d7fffh ba25 0 1 1 0 0 1 x x x 64/32 190000h-19ffffh 0c8000h-0cffffh ba24 0 1 1 0 0 0 x x x 64/32 180000h-18ffffh 0c0000h-0c7fffh ba23 0 1 0 1 1 1 x x x 64/32 170000h-17ffffh 0b8000h-0bffffh ba22 0 1 0 1 1 0 x x x 64/32 160000h-16ffffh 0b0000h-0b7fffh ba21 0 1 0 1 0 1 x x x 64/32 150000h-15ffffh 0a8000h-0affffh ba20 0 1 0 1 0 0 x x x 64/32 140000h-14ffffh 0a0000h-0a7fffh ba19 0 1 0 0 1 1 x x x 64/32 130000h-13ffffh 098000h-09ffffh ba18 0 1 0 0 1 0 x x x 64/32 120000h-12ffffh 090000h-097fffh ba17 0 1 0 0 0 1 x x x 64/32 110000h-11ffffh 088000h-08ffffh ba16 0 1 0 0 0 0 x x x 64/32 100000h-10ffffh 080000h-087fffh ba15 0 0 1 1 1 1 x x x 64/32 0f0000h-0fffffh 078000h-07ffffh ba14 0 0 1 1 1 0 x x x 64/32 0e0000h-0effffh 070000h-077fffh ba13 0 0 1 1 0 1 x x x 64/32 0d0000h-0dffffh 068000h-06ffffh ba12 0 0 1 1 0 0 x x x 64/32 0c0000h-0cffffh 060000h-067fffh ba11 0 0 1 0 1 1 x x x 64/32 0b0000h-0bffffh 058000h-05ffffh ba10 0 0 1 0 1 0 x x x 64/32 0a0000h-0affffh 050000h-057fffh ba9 0 0 1 0 0 1 x x x 64/32 090000h-09ffffh 048000h-04ffffh ba8 0 0 1 0 0 0 x x x 64/32 080000h-08ffffh 040000h-047fffh ba7 0 0 0 1 1 1 x x x 64/32 070000h-07ffffh 038000h-03ffffh ba6 0 0 0 1 1 0 x x x 64/32 060000h-06ffffh 030000h-037fffh ba5 0 0 0 1 0 1 x x x 64/32 050000h-05ffffh 028000h-02ffffh ba4 0 0 0 1 0 0 x x x 64/32 040000h-04ffffh 020000h-027fffh ba3 0 0 0 0 1 1 x x x 64/32 030000h-03ffffh 018000h-01ffffh ba2 0 0 0 0 1 0 x x x 64/32 020000h-02ffffh 010000h-017fffh ba1 0 0 0 0 0 1 x x x 64/32 010000h-01ffffh 008000h-00ffffh ba0 0 0 0 0 0 0 x x x 64/32 000000h-00ffffh 000000h-007fffh table 2. secode block addresses for top boot devices device block address a20-a12 block size (x8) address range (x16) address range k5a3280yt/k5a3380yt 111111xxx 64/32 3f0000h-3fffffh 1f8000h-1ff f ffh
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 6 - preliminary table 3. flash memory bottom boot block address (k5a3280yb/k5a3380yb) k5 a3280 yb k5 a3380 yb block block address block size (kb/kw) address range a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode bank2 bank2 ba70 1 1 1 1 1 1 x x x 64/32 3f0000h-3fffffh 1f8000h-1f f fffh ba69 1 1 1 1 1 0 x x x 64/32 3e0000h-3effffh 1f0000h-1f7fffh ba68 1 1 1 1 0 1 x x x 64/32 3d0000h-3dffffh 1e8000h-1effffh ba67 1 1 1 1 0 0 x x x 64/32 3c0000h-3cffffh 1e0000h-1e7fffh ba66 1 1 1 0 1 1 x x x 64/32 3b0000h-3bffffh 1d8000h-1dffffh ba65 1 1 1 0 1 0 x x x 64/32 3a0000h-3affffh 1d0000h-1d7fffh ba64 1 1 1 0 0 1 x x x 64/32 390000h-39ffffh 1c8000h-1cffffh ba63 1 1 1 0 0 0 x x x 64/32 380000h-38ffffh 1c0000h-1c7fffh ba62 1 1 0 1 1 1 x x x 64/32 370000h-37ffffh 1b8000h-1bffffh ba61 1 1 0 1 1 0 x x x 64/32 360000h-36ffffh 1b0000h-1b7fffh ba60 1 1 0 1 0 1 x x x 64/32 350000h-35ffffh 1a8000h-1affffh ba59 1 1 0 1 0 0 x x x 64/32 340000h-34ffffh 1a0000h-1a7fffh ba58 1 1 0 0 1 1 x x x 64/32 330000h-33ffffh 198000h-19ffffh ba57 1 1 0 0 1 0 x x x 64/32 320000h-32ffffh 190000h-197fffh ba56 1 1 0 0 0 1 x x x 64/32 310000h-31ffffh 188000h-18ffffh ba55 1 1 0 0 0 0 x x x 64/32 300000h-30ffffh 180000h-187fffh ba54 1 0 1 1 1 1 x x x 64/32 2f0000h-2f1fffh 178000h-17ffffh ba53 1 0 1 1 1 0 x x x 64/32 2e0000h-2effffh 170000h-177fffh ba52 1 0 1 1 0 1 x x x 64/32 2d0000h-2dffffh 168000h-16ffffh ba51 1 0 1 1 0 0 x x x 64/32 2c0000h-2cffffh 160000h-167fffh ba50 1 0 1 0 1 1 x x x 64/32 2b0000h-2bffffh 158000h-15ffffh ba49 1 0 1 0 1 0 x x x 64/32 2a0000h-2affffh 150000h-157fffh ba48 1 0 1 0 0 1 x x x 64/32 290000h-29ffffh 148000h-14ffffh ba47 1 0 1 0 0 0 x x x 64/32 280000h-28ffffh 140000h-147fffh ba46 1 0 0 1 1 1 x x x 64/32 270000h-27ffffh 138000h-13ffffh ba45 1 0 0 1 1 0 x x x 64/32 260000h-26ffffh 130000h-137fffh ba44 1 0 0 1 0 1 x x x 64/32 250000h-25ffffh 128000h-12ffffh ba43 1 0 0 1 0 0 x x x 64/32 240000h-24ffffh 120000h-127fffh ba42 1 0 0 0 1 1 x x x 64/32 230000h-23ffffh 118000h-11ffffh ba41 1 0 0 0 1 0 x x x 64/32 220000h-22ffffh 110000h-117fffh ba40 1 0 0 0 0 1 x x x 64/32 210000h-21ffffh 108000h-10ffffh ba39 1 0 0 0 0 0 x x x 64/32 200000h-20ffffh 100000h-107fffh ba38 0 1 1 1 1 1 x x x 64/32 1f0000h-1fffffh 0f8000h-0fffffh ba37 0 1 1 1 1 0 x x x 64/32 1e0000h-1effffh 0f0000h-0f7fffh ba36 0 1 1 1 0 1 x x x 64/32 1d0000h-1dffffh 0e8000h-0effffh ba35 0 1 1 1 0 0 x x x 64/32 1c0000h-1cffffh 0e0000h-0e7fffh
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 7 - preliminary table 3. flash memory bottom boot block address (k5a3280yb/k5a3380yb) note: the address range is a20 ~ a-1 in the byte mode ( byte f = v il ) or a20 ~ a0 in the word mode ( byte f = v ih ). the bank address bits is a20 ~ a19 for k5a3280yb, a20 for k5a3380yb. k5 a3280 yb k5 a3380 yb block block address block size (kb/kw) address range a20 a19 a18 a17 a16 a15 a14 a13 a12 byte mode word mode bank2 bank1 ba34 0 1 1 0 1 1 x x x 64/32 1b0000h-1bffffh 0d8000h-0dffffh ba33 0 1 1 0 1 0 x x x 64/32 1a0000h-1affffh 0d0000h-0d7fffh ba32 0 1 1 0 0 1 x x x 64/32 190000h-19ffffh 0c8000h-0cffffh ba31 0 1 1 0 0 0 x x x 64/32 180000h-18ffffh 0c0000h-0c7fffh ba30 0 1 0 1 1 1 x x x 64/32 170000h-17ffffh 0b8000h-0bffffh ba29 0 1 0 1 1 0 x x x 64/32 160000h-16ffffh 0b0000h-0b7fffh ba28 0 1 0 1 0 1 x x x 64/32 150000h-15ffffh 0a8000h-0affffh ba27 0 1 0 1 0 0 x x x 64/32 140000h-14ffffh 0a0000h-0a7fffh ba26 0 1 0 0 1 1 x x x 64/32 130000h-13ffffh 098000h-09ffffh ba25 0 1 0 0 1 0 x x x 64/32 120000h-12ffffh 090000h-097fffh ba24 0 1 0 0 0 1 x x x 64/32 110000h-11ffffh 088000h-08ffffh ba23 0 1 0 0 0 0 x x x 64/32 100000h-10ffffh 080000h-087fffh bank1 ba22 0 0 1 1 1 1 x x x 64/32 0f0000h-0fffffh 078000h-07ffffh ba21 0 0 1 1 1 0 x x x 64/32 0e0000h-0effffh 070000h-077fffh ba20 0 0 1 1 0 1 x x x 64/32 0d0000h-0dffffh 068000h-06ffffh ba19 0 0 1 1 0 0 x x x 64/32 0c0000h-0cffffh 060000h-067fffh ba18 0 0 1 0 1 1 x x x 64/32 0b0000h-0bffffh 058000h-05ffffh ba17 0 0 1 0 1 0 x x x 64/32 0a0000h-0affffh 050000h-057fffh ba16 0 0 1 0 0 1 x x x 64/32 090000h-09ffffh 048000h-04ffffh ba15 0 0 1 0 0 0 x x x 64/32 080000h-08ffffh 040000h-047fffh ba14 0 0 0 1 1 1 x x x 64/32 070000h-07ffffh 038000h-03ffffh ba13 0 0 0 1 1 0 x x x 64/32 060000h-06ffffh 030000h-037fffh ba12 0 0 0 1 0 1 x x x 64/32 050000h-05ffffh 028000h-02ffffh ba11 0 0 0 1 0 0 x x x 64/32 040000h-04ffffh 020000h-027fffh ba10 0 0 0 0 1 1 x x x 64/32 030000h-03ffffh 018000h-01ffffh ba9 0 0 0 0 1 0 x x x 64/32 020000h-02ffffh 010000h-017fffh ba8 0 0 0 0 0 1 x x x 64/32 010000h-01ffffh 008000h-00ffffh ba7 0 0 0 0 0 0 1 1 1 8/4 00e000h-00ffffh 007000h-007fffh ba6 0 0 0 0 0 0 1 1 0 8/4 00c000h-00dfffh 006000h-006fffh ba5 0 0 0 0 0 0 1 0 1 8/4 00a000h-00bfffh 005000h-005fffh ba4 0 0 0 0 0 0 1 0 0 8/4 008000h-009fffh 004000h-004fffh ba3 0 0 0 0 0 0 0 1 1 8/4 006000h-007fffh 003000h-003fffh ba2 0 0 0 0 0 0 0 1 0 8/4 004000h-005fffh 002000h-002fffh ba1 0 0 0 0 0 0 0 0 1 8/4 002000h-003fffh 001000h-001fffh ba0 0 0 0 0 0 0 0 0 0 8/4 000000h-001fffh 000000h-000fffh table 4. secode block addresses for bottom boot devices device block address a20-a12 block size (x8) address range (x16) address range k5a3280yb/k5a3380yb 000000xxx 64/32 000000h-00ffffh 000000h- 0 07f f fh
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 8 - preliminary flash memory command definitions flash memory operates by selecting and executing its operational modes. each operational mode has its own command set. in order to select a certain mode, a proper command with specific address and data sequences must be written into the command register. writing incorrect information which include address and data or writing an improper command will reset the device to the read mo de. the defined valid register command sequences are stated in table 5. note that erase suspend (b0h) and erase resume (30h) commands are valid only while the block erase operation is in progress. table 5. command sequences command sequence cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle word byte word byte word byte word byte word byte word byte read addr 1 ra data rd reset addr 1 xxxh data f0h autoselect manufacturer id (2,3) addr 4 555h aaah 2aah 555h da/ 555h da/ aaah da/ x00h da/ x00h data aah 55h 90h ech autoselect device code (2,3) addr 4 555h aaah 2aah 555h da/ 555h da/ aaah da/ x01h da/ x02h data aah 55h 90h (see table 6) autoselect block group protect verify (2,3) addr 4 555h aaah 2aah 555h da/ 555h da/ aaah ba / x02h ba/ x04h data aah 55h 90h (see table 6) auto select secode block factory protect verify (2,3) addr 4 555h aaah 2aah 555h da/ 555h da/ aaah da / x03h da/ x06h data aah 55h 90h (see table 6) enter secode block region addr 3 555h aaah 2aah 555h 555h aaah data aah 55h 88h exit secode block region addr 4 555h aaah 2aah 555h 555h aaah xxxh data aah 55h 90h 00h program addr 4 555h aaah 2aah 555h 555h aaah pa data aah 55h a0h pd unlock bypass addr 3 555h aaah 2aah 555h 555h aaah data aah 55h 20h unlock bypass program addr 2 xxxh pa data a0h pd unlock bypass reset addr 2 xxxh xxxh data 90h 00h chip erase addr 6 555h aaah 2aah 555h 555h aaah 555h aaah 2aah 555h 555h aaah data aah 55h 80h aah 55h 10h block erase addr 6 555h aaah 2aah 555h 555h aaah 555h aaah 2aah 555h ba data aah 55h 80h aah 55h 30h block erase suspend (4, 5) addr 1 xxxh data b0h block erase resume addr 1 xxxh data 30h
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 9 - preliminary notes: 1. ra : read address, pa : program address, rd : read data, pd : program data da : dual bank address (a19 - a20), ba : block address (a12 - a20), x = don?t care . 2. to terminate the autoselect mode, it is necessary to write reset command to the register. 3. the 4th cycle data of autoselect mode is output data. the 3rd and 4th cycle bank addresses of autoselect mode must be same. 4. the read / program operations at non-erasing blocks and the autoselect mode are allowed in the erase suspend mode. 5. the erase suspend command is applicable only to the block erase operation. 6. dq8 - dq15 are don?t care in command sequence, except for rd and pd. 7. a11 - a20 are also don?t care, except for the case of special notice. table 6. flash memory autoselect codes description dq8 to dq15 dq7 to dq0 byte f = v ih byte f = v il manufacturer id x x ech device code k5a3280yt (top boot block) 22h x a0h device code k5a3280yb (bottom boot block) 22h x a2h device code k5a3380yt (top boot block) 22h x a1h device code k5a3380yb (bottom boot block) 22h x a3h block protection verification x x 01h (protected), 00h (unprotected) secode block indicator bit (dq7) x x 80h (factory locked), 00h (not factory locked) table 7. flash memory operation table notes: 1. l = v il (low), h = v ih (high), v id = 8.5v~12.5v, d in = data in, d out = data out, x = don't care. 2. wp /acc and reset ball are asserted at vcc f 0.3 v or vss 0.3 v in the stand-by mode. 3. addresses must be composed of the block address (a12 - a20). the block protect and unprotect operations may be implemented via programming equipment too. refer to the "block group protection and unprotection". 4. if wp /acc = v il, the two outermost boot blocks is protected. if wp /acc = v ih, the two outermost boot block protection depends on whether those blocks were last protected or unprotected using the method described in "block group protection and unprotection". if wp /acc = v hh , all blocks will be temporarily unprotected. operation ce f oe we byte f wp / acc a9 a6 a1 a0 dq15/ a-1 dq8/ dq14 dq0/ dq7 reset read word l l h h l/h a9 a6 a1 a0 dq15 d out d out h byte l l h l a9 a6 a1 a0 a-1 high-z d out h stand-by vcc f 0.3v x x x (2) x x x x high-z high-z high-z (2) output disable l h h x l/h x x x x high-z high-z high-z h reset x x x x l/h x x x x high-z high-z high-z l write word l h l h (4) a9 a6 a1 a0 d in d in d in h byte l h l l a9 a6 a1 a0 a-1 high-z d in h enable block group protect (3) l h l x l/h x l h l x x d in v id enable block group unprotect (3) l h l x (4) x h h l x x d in v id temporary block group x x x x (4) x x x x x x x v id
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 10 - preliminary table 8. sram operation table 1. word mode note : x means don t care. (must be low or high state) 2. byte mode note : x means don t care. (must be low or high state) dnu = do not use 1) address input for byte operation. cs 1 s cs2 s oe we byte s sa lb ub d/q0~7 d/q8~15 mode power h x x x x x x x high-z high-z deselected standby x l x x x x x x high-z high-z deselected standby x x x x x x h h high-z high-z deselected standby l h h h vcc s x l x high-z high-z output disabled active l h h h vcc s x x l high-z high-z output disabled active l h l h vcc s x l h dout high-z lower byte read active l h l h vcc s x h l high-z dout upper byte read active l h l h vcc s x l l dout dout word read active l h x l vcc s x l h din high-z lower byte write active l h x l vcc s x h l high-z din upper byte write active l h x l vcc s x l l din din word write active cs 1 s cs2 s oe we byte s sa lb ub d/q0~7 d/q8~15 mode power h x x x x x x x high-z high-z deselected standby x l x x x x x x high-z high-z deselected standby l h h h v ss sa 1) dnu dnu high-z dnu output disabled active l h l h v ss sa 1) dnu dnu dout dnu lower byte read active l h x l v ss sa 1) dnu dnu din dnu lower byte write active
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 11 - preliminary flash device operation byte/word mode if the byte f ball is set at logical "1" , the device is in word mode, dq0-dq15 are active. otherwise the byte f ball is set at logical "0" , the device is in byte mode, dq0-dq7 are active. dq8-dq14 are in the high-z state and dq15 ball is used as an input for the lsb (a-1) address ball. read mode flash memory is controlled by chip enable ( ce f ), output enable ( oe ) and write enable ( we ). when ce f and oe are low and we is high, the data stored at the specified address location,will be the output of the device. the outputs are in high impedance s tate whenever ce f or oe is high. standby mode flash memory features stand-by mode to reduce power consumption. this mode puts the device on hold when the device is dese- lected by making ce f high ( ce f = v ih ). refer to the dc characteristics for more details on stand-by modes. output disable the device outputs are disabled when oe is high ( oe = v ih ). the output balls are in high impedance state. automatic sleep mode flash memory features automatic sleep mode to minimize the device power consumption. since the device typically draws 5 m a of current in automatic sleep mode, this feature plays an extremely important role in battery-powered applications. when addresses remain steady for t aa +50ns, the device automatically activates the automatic sleep mode. in the sleep mode, output data is latched and always available to the system. when addresses are changed, the device provides new data without wait time. data outputs t aa + 50ns data auto sleep mode address data data data data autoselect mode flash memory offers the autoselect mode to identify manufacturer and device type by reading a binary code. the autoselect mode allows programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. in addition, this mode allows the verification of the status of write protected blocks. the manufacturer and device code can be read via the command register. the command sequence is shown in table 5 and figure 3. the autoselect operation of block protect ver- ification is initiated by first writing two unlock cycle. the third cycle must contain the bank address and autoselect command ( 90h). if block address while (a6, a1, a0) = (0,1,0) is finally asserted on the address ball, it will produce a logical "1" at the device output dq0 to indicate a write protected block or a logical "0" at the device output dq0 to indicate a write unprotected block. to termina te the autoselect operation, write reset command (f0h) into the command register. figure 2. auto sleep mode operation
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 12 - preliminary figure 3. autoselect operation we 555h/ aaah 2aah/ 555h 555h/ aaah aah 55h 90h 00h/ 01h/ ech manufacturer code device code a20 ~ a0(x16)/* dq15 ~ dq0 f0h return to read mode 22a0h or 22a2h note: the 3rd cycle and 4th cycle address must include the same bank address. please refer to table 6 for device code. (k5a3280y) a20 ~ a-1(x8) 00h 02h write (program/erase) mode flash memory executes its program/erase operations by writing commands into the command register. in order to write the com- mands to the register, ce f and we must be low and oe must be high. addresses are latched on the falling edge of ce f or we (whichever occurs last) and the data are latched on the rising edge of ce f or we (whichever occurs first). the device uses standard microprocessor write timing. program flash memory can be programmed in units of a word or a byte. programming is writing 0's into the memory array by executing the internal program routine. in order to perform the internal program routine, a four-cycle command sequence is necessary. the firs t two cycles are unlock cycles. the third cycle is assigned for the program setup command. in the last cycle, the address of the m em- ory location and the data to be programmed at that location are written. the device automatically generates adequate program pulses and verifies the programmed cell margin by the internal program routine. during the execution of the routine, the system is not required to provide further controls or timings. during the internal program routine, commands written to the device will be ignored. note that a hardware reset during a program operation will cause data corruption at the corresponding location. figure 4. program command sequence we 555h/ aaah 2aah/ 555h 555h/ aaah aah 55h a0h program program program start dq15-dq0 address data ry/ by a20 ~ a0(x16)/ a20 ~ a-1(x8)
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 13 - preliminary unlock bypass flash memory provides the unlock bypass mode to save its program time. the mode is invoked by the unlock bypass command sequence. unlike the standard program command sequence that contains four bus cycles, the unlock bypass program command sequence comprises only two bus cycles. the unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. writ- ing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20h). once the device is in the unlock bypass mode, the unlock bypass program command sequence is necessary to program in this mode. the unlock bypass program command sequence is comprised of only two bus cycles; writing the unlock bypass program command (a0h) is followed by the pro- gram address and data. this command sequence is the only valid one for programming the device in the unlock bypass mode. the unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. the unlock bypass reset command sequence consists of two bus cycles. the first cycle must contain the data (90h). the second cycle contains only the data (00h). then, the device returns to the read mode chip erase to erase a chip is to write 1 s into the entire memory array by executing the internal erase routine. the chip erase requires six bus cycles to write the command sequence. the erase set-up command is written after first two "unlock" cycles. then, there are two more write cycles prior to writing the chip erase command. the internal erase routine automatically pre-programs and verifies th e entire memory for an all zero data pattern prior to erasing. the automatic erase begins on the rising edge of the last we or ce f pulse in the command sequence and terminates when dq7 is "1". after that the device returns to the read mode. figure 5. chip erase command sequence we 555h/ aaah 2aah/ 555h 555h/ aaah aah 55h 80h 555h chip erase start dq15-dq0 aaah 2aah/ 555h aah 55h 10h ry/ by 555h/ aaah block erase to erase a block is to write 1 s into the desired memory block by executing the internal erase routine. the block erase requires six bus cycles to write the command sequence shown in table 5. after the first two "unlock" cycles, the erase setup command (80h) is written at the third cycle. then there are two more "unlock" cycles followed by the block erase command. the internal erase rout ine automatically pre-programs and verifies the entire memory prior to erasing it. the block address is latched on the falling edge of we or ce f , while the block erase command is latched on the rising edge of we or ce f . multiple blocks can be erased sequentially by writing the six bus-cycle operation in fig 6. upon completion of the last cycle fo r the block erase, additional block address and the block erase command (30h) can be written to perform the multi-block erase. an 50 us (typical) "time window" is required between the block erase command writes. the block erase command must be written within the 50 us "time window", otherwise the block erase command will be ignored. the 50 us "time window" is reset when the falling edge of the we occurs within the 50 us of "time window" to latch the block erase command. during the 50 us of "time window", any command other than the block erase or the erase suspend command written to the device will reset the device to read mode. after the 50 u s of "time window", the block erase command will initiate the internal erase routine to erase the selected blocks. any block erase address and command following the exceeded "time window" may or may not be accepted. no other commands will be recognized except the erase suspend command. a20 ~ a0(x16)/ a20 ~ a-1(x8)
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 14 - preliminary we 555h/ aaah 2aah/ 555h 555h/ aaah aah 55h 80h 555h/ block erase start dq15-dq0 aaah 2aah/ 555h block address aah 55h 30h ry/ by we dq15-dq0 figure 7. erase suspend/resume command sequence erase suspend / resume the erase suspend command interrupts the block erase to read or program data in a block that is not being erased. the erase sus- pend command is only valid during the block erase operation including the time window of 50 us. the erase suspend command is not valid while the chip erase or the internal program routine sequence is running. when the erase suspend command is written during a block erase operation, the device requires a maximum of 20 us to suspend the erase operation. but, when the erase suspend command is written during the block erase time window (50 us) , the device immediately terminates the block erase time window and suspends the erase operation. after the erase operation has been suspended, the device is availble for reading or programming data in a block that is not bein g erased. the system may also write the autoselect command sequence when the device is in the erase suspend mode. when the erase resume command is executed, the block erase operation will resume. when the erase suspend or erase resume command is executed, the addresses are in don't care state. figure 6. block erase command sequence a20 ~ a0(x16)/ a20 ~ a-1(x8) a20 ~ a0(x16)/ a20 ~ a-1(x8) 555h/ aaah block address aah 30h xxxh erase resume xxxh b0h 30h erase suspend block erase start block erase command sequence
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 15 - preliminary read while write flash memory provides dual bank memory architecture that divides the memory array into two banks. the device is capable of read- ing data from one bank and writing data to the other bank simultaneously. this is so called the read while write operation with dual bank architecture; this feature provides the capability of executing the read operation during program/erase or erase-suspend-pr o- gram operation . the read while write operation is prohibited during the chip erase operation. it is also allowed during erase operation when eit her single block or multiple blocks from same bank are loaded to be erased. it means that the read while write operation is prohibited when blocks from bank1 and another blocks from bank2 are loaded all together for the m ulti-block erase operation. block group protection & unprotection flash memory feature hardware block group protection. this feature will disable both program and erase operations in any combina - tion of twenty five block groups of memory. please refer to tables 10 and 11. the block group protection feature is enabled usin g programming equipment at the user?s site. the device is shipped with all block groups unprotected. this feature can be hardware protected or unprotected. if a block is protected, program or erase command in the protected block will be ignored by the device. the protected block can only be read. this is useful method to preserve an important program data. the block group unprotection allows the protected blocks to be erased or programed. all blocks must be protected before unprotect op er- ation is executing. the block protection and unprotection can be implemented by the following method. table 9. block group protection & unprotection operation ce f oe we byte f a9 a6 a1 a0 dq15/ a-1 dq8/ dq14 dq0/ dq7 reset block group protect l h l x x l h l x x d in v id block group unprotect l h l x x h h l x x d in v id address must be inputted to the block group address (a12~a20) during block group protection operation. please refer to figure 9 (algorithm) and switching waveforms of block group protect & unprotect operations. temporary block group unprotect the protected blocks of the flash memory can be temporarily unprotected by applying high voltage (v id = 8.5v~12.5v) to the reset ball. in this mode, previously protected blocks can be programmed or erased with the program or erase command routines. when the reset ball goes high ( reset = v ih ), all the previously protected blocks will be protected again. if the wp /acc ball is asserted at v il , the two outermost boot blocks remain protected. reset program & erase operation v id v = v ih or v il at protected block ce f we figure 8. temporary block group unprotect sequence
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 16 - preliminary figure 9. block group protection & unprotection algorithms note: all blocks must be protected before unprotect operation is executing. block protect algorithm set up block group address block group protect: write 60h to block group address with a6=0,a1=1 a0=0 wait 150 m s verify block group protect:write 40h to block group address with a6=0, a1=1,a0=0 read from block group address with a6=0, a1=1,a0=0 data=01h? protect another block group ? remove v id from reset write reset command end wait 1 m s first write cycle=60h? temporary block group unprotect mode block group unprotect write 60h with a6=1,a1=1 a0=0 wait 15ms verify block group unprotect:write 40h to block group address with a6= 1 , a1=1,a0=0 read from block group address with a6=1, a1=1,a0=0 data=00h? last block group remove v id from reset write reset command end no increment count count =1000? device failed no yes yes no no yes algorithm increment count count =25? device failed no yes no all block group s protected ? no block group , i= 0 start count = 1 reset =v id yes yes yes no verified ? block group protection ? yes no yes set up next block reset count=1 block unprotect group address
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 17 - preliminary table 10. flash memory block group address (top boot block) block group block address block a20 a19 a18 a17 a16 a15 a14 a13 a12 bga0 0 0 0 0 0 0 x x x ba0 bga1 0 0 0 0 0 1 x x x ba1 to ba3 1 0 1 1 bga2 0 0 0 1 x x x x x ba4 to ba7 bga3 0 0 1 0 x x x x x ba8 to ba11 bga4 0 0 1 1 x x x x x ba12 to ba15 bga5 0 1 0 0 x x x x x ba16 to ba19 bga6 0 1 0 1 x x x x x ba20 to ba23 bga7 0 1 1 0 x x x x x ba24 to ba27 bga8 0 1 1 1 x x x x x ba28 to ba31 bga9 1 0 0 0 x x x x x ba32 to ba35 bga10 1 0 0 1 x x x x x ba36 to ba39 bga11 1 0 1 0 x x x x x ba40 to ba43 bga12 1 0 1 1 x x x x x ba44 to ba47 bga13 1 1 0 0 x x x x x ba48 to ba51 bga14 1 1 0 1 x x x x x ba52 to ba55 bga15 1 1 1 0 x x x x x ba56 to ba59 bga16 1 1 1 1 0 0 x x x ba60 to ba62 0 1 1 0 bga17 1 1 1 1 1 1 0 0 0 ba63 bga18 1 1 1 1 1 1 0 0 1 ba64 bga19 1 1 1 1 1 1 0 1 0 ba65 bga20 1 1 1 1 1 1 0 1 1 ba66 bga21 1 1 1 1 1 1 1 0 0 ba67 bga22 1 1 1 1 1 1 1 0 1 ba68 bga23 1 1 1 1 1 1 1 1 0 ba69 bga24 1 1 1 1 1 1 1 1 1 ba70
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 18 - preliminary table 11. flash memory block group address (bottom boot block) block group block address block a20 a19 a18 a17 a16 a15 a14 a13 a12 bga0 0 0 0 0 0 0 0 0 0 ba0 bga1 0 0 0 0 0 0 0 0 1 ba1 bga2 0 0 0 0 0 0 0 1 0 ba2 bga3 0 0 0 0 0 0 0 1 1 ba3 bga4 0 0 0 0 0 0 1 0 0 ba4 bga5 0 0 0 0 0 0 1 0 1 ba5 bga6 0 0 0 0 0 0 1 1 0 ba6 bga7 0 0 0 0 0 0 1 1 1 ba7 bga8 0 0 0 0 0 1 x x x ba8 to ba10 1 0 1 1 bga9 0 0 0 1 x x x x x ba11 to ba14 bga10 0 0 1 0 x x x x x ba15 to ba18 bga11 0 0 1 1 x x x x x ba19 to ba22 bga12 0 1 0 0 x x x x x ba23 to ba26 bga13 0 1 0 1 x x x x x ba27 to ba30 bga14 0 1 1 0 x x x x x ba31 to ba34 bga15 0 1 1 1 x x x x x ba35 to ba38 bga16 1 0 0 0 x x x x x ba39 to ba42 bga17 1 0 0 1 x x x x x ba43 to ba46 bga18 1 0 1 0 x x x x x ba47 to ba50 bga19 1 0 1 1 x x x x x ba51 to ba54 bga20 1 1 0 0 x x x x x ba55 to ba58 bga21 1 1 0 1 x x x x x ba59 to ba62 bga22 1 1 1 0 x x x x x ba63 to ba66 bga23 1 1 1 1 0 0 x x x ba67 to ba69 0 1 1 0 bga24 1 1 1 1 1 1 x x x ba70
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 19 - preliminary write protect ( wp ) the wp /acc ball has two useful functions. the one is that certain boot block is protected by the hardware method not to use v id . the other is that program operation is accelerated to reduce the program time (refer to accelerated program operation paragraph) . when the wp /acc ball is asserted at v il , the device can not perform program and erase operation in the two "outermost" 8k byte boot blocks independently of whether those blocks were protected or unprotected using the method described in "block group pro- tection/unprotection". the write protected blocks can only be read. this is useful method to preserve an important program data. the two outermost 8k byte boot blocks are the two blocks containing the lowest addresses in a bottom-boot-configured device, or the two blocks containing the highest addresses in a top-boot-congfigured device. (k5a3280yt/k5a3380yt : ba69 and ba70, k5a3280yb/k5a3380yb : ba0 and ba1) when the wp /acc ball is asserted at v ih , the device reverts to whether the two outermost 8k byte boot blocks were last set to be protected or unprotected. that is, block protection or unprotection for these two blocks depends on whether they were last prote cted or unprotected using the method described in "block group protection/unprotection". recommend that the wp /acc ball must not be in the state of floating or unconnected, or the device may be led to malfunction. secode(security code) block region the secode block feature provides a flash memory region to be stored unique and permanent identification code, that is, electron ic serial number (esn), customer code and so on. this is primarily intended for customers who wish to use an electronic serial num - ber (esn) in the device with the esn protected against modification. once the secode block region is protected, any further modifi- cation of that region is impossible. this ensures the security of the esn once the product is shipped to the field. the secode block is factory locked or customer lockable. before the device is shipped, the factory locked secode block is writte n on the special code and it is protected. the secode indicator bit (dq7) is permanently fixed at "1" and it is not changed. the customer lockable secode block is unprotected, therefore it is programmed and erased. the secode indicator bit (dq7) of it is permanently fixed at "0" and it is not changed. but once it is protected, there is no procedure to unprotect and modify the secode block. the secode block region is 64k bytes in length and is accessed through a new command sequence (see table 5). after the system has written the enter secode block command sequence, the system may read the secode block region by using the same addresses of the boot blocks (8kbx8). the k5a3280yt/k5a3380yt occupies the address of the byte mode 3f0000h to 3fffffh (word mode 1f8000h to 1fffffh) and the k5a3280yb/k5a3380yb type occupies the address of the byte mode 000000h to 00ffffh (word mode 000000h to 007fffh). this mode of operation continues until the system issues the exit secode block com- mand sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to read mode. accelerated program operation accelerated program operation reduces the program time. this is one of two functions provided by the wp /acc ball. when the wp / acc ball is asserted as v hh , the device automatically enters the aforementioned unlock bypass mode, temporarily unprotecting any protected blocks, and reduces the program operation time. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp /acc ball returns the device to normal operation. recommend that the wp /acc ball must not be asserted at v hh except accelerated program operation, or the device may be damaged. in addition, the wp /acc ball must not be in the state of floating or unconnected, otherwise the device may be led to mal- function. software reset the reset command provides that the device is reseted to read mode or erase-suspend-read mode. the addresses are in don't care state. the reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a pro- gram command sequence before programming begins. this resets the bank in which was operating to read mode. if the device is be erasing or programming, the reset command is invalid until the operation is completed. also, the reset command is valid between the sequence cycles in an autoselect command sequence. in the autoselect mode, the reset command returns the bank to read mode. if a bank entered the autoselect mode in the erase suspend mode, the reset command returns the bank to erase-suspend-read mode. if dq5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode if the bank was in the erase suspend state.
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 20 - preliminary hardware reset flash memory offers a reset feature by driving the reset ball to v il . the reset ball must be kept low (v il ) for at least 500ns. when the reset ball is driven low, any operation in progress will be terminated and the internal state machine will be reset to the standby mode after 20us. if a hardware reset occurs during a program operation, the data at that particular location will be lo st. once the reset ball is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. also, note that all the data output balls are tri-stated for the duration of the reset pulse. the reset ball may be tied to the system reset ball. if a system reset occurs during the internal program and erase routine, the device will be automatically reset to the read mode ; this will enable the systems microprocessor to read the boot-up firmware f rom the flash memory. power-up protection to avoid initiation of a write cycle during vcc f power-up, reset low must be asserted during power-up. after reset goes high, the device is reset to the read mode. low vcc f write inhibit to avoid initiation of a write cycle during vcc f power-up and power-down, a write cycle is locked out for vcc f less than 1.8v. if vcc f < v lko (lock-out voltage), the command register and all internal program/erase circuits are disabled. under this condition the device will reset itself to the read mode. subsequent writes will be ignored until the vcc f level is greater than v lko . it is the user s responsi- bility to ensure that the control balls are logically correct to prevent unintentional writes when vcc f is above 1.8v. write pulse glitch protection noise pulses of less than 5ns(typical) on ce f , oe , or we will not initiate a write cycle. logical inhibit writing is inhibited under any one of the following conditions : oe = v il , ce f = v ih or we = v ih . to initiate a write, ce f and we must be "0", while oe is "1". commom flash memory interface common flash momory interface is contrived to increase the compatibility of host system software. it provides the specific info rma- tion of the device, such as memory size, byte/word configuration, and electrical features. once this information has been obtain ed, the system software will know which command sets to use to enable flash writes, block erases, and control the flash component. when the system writes the cfi command(98h) to address 55h in word mode(or address aah in byte mode), the device enters the cfi mode. and then if the system writes the address shown in table 12, the system can read the cfi data. query data are always presented on the lowest-order data outputs(dq0-7) only. in word(x16) mode, the upper data outputs(dq8-15) is 00h. to terminate this operation, the system must write the reset command.
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 21 - preliminary table 12. common flash memory interface code description addresses (word mode) addresses (byte mode) data query unique ascii string "qry" 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h primary oem command set 13h 14h 26h 28h 0002h 0000h address for primary extended table 15h 16h 2ah 2ch 0040h 0000h alternate oem command set (00h = none exists) 17h 18h 2eh 30h 0000h 0000h address for alternate oem extended table (00h = none exists) 19h 1ah 32h 34h 0000h 0000h vcc min. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1bh 36h 0027h vcc max. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1ch 38h 0036h vpp min. voltage(00h = no vpp pin present) 1dh 3ah 0000h vpp max. voltage(00h = no vpp pin present) 1eh 3ch 0000h typical timeout per single byte/word write 2 n us 1fh 3eh 0004h typical timeout for min. size buffer write 2 n us(00h = not supported) 20h 40h 0000h typical timeout per individual block erase 2 n ms 21h 42h 000ah typical timeout for full chip erase 2 n ms(00h = not supported) 22h 44h 0000h max. timeout for byte/word write 2 n times typical 23h 46h 0005h max. timeout for buffer write 2 n times typical 24h 48h 0000h max. timeout per individual block erase 2 n times typical 25h 4ah 0004h max. timeout for full chip erase 2 n times typical(00h = not supported) 26h 4ch 0000h device size = 2 n byte 27h 4eh 0016h flash device interface description 28h 29h 50h 52h 0002h 0000h max. number of byte in multi-byte write = 2 n 2ah 2bh 54h 56h 0000h 0000h number of erase block regions within device 2ch 58h 0002h erase block region 1 information 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0007h 0000h 0020h 0000h erase block region 2 information 31h 32h 33h 34h 62h 64h 66h 68h 003eh 0000h 0000h 0001h erase block region 3 information 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 4 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 22 - preliminary table 12. common flash memory interface code note : 1. the number of blocks in bank2 is device dependent. k5a3280y(8mb/24mb) = 30h (48blocks) k5a3380y(16mb/16mb) = 20h (32blocks) description addresses (word mode) addresses (byte mode) data query-unique ascii string "pri" 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h major version number, ascii 43h 86h 0033h minor version number, ascii 44h 88h 0033h address sensitive unlock(bits 1-0) 0 = required, 1= not required silcon revision number(bits 7-2) 45h 8ah 0000h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 46h 8ch 0002h block protect 0 = not supported, 1 = number of blocks in per group 47h 8eh 0001h block temporary unprotect 00 = not supported, 01 = supported 48h 90h 0001h block protect/unprotect scheme 04=k8d1x16u mode 49h 92h 0004h simultaneous operation (1) 00 = not supported, xx = number of blocks in bank2 4ah 94h 00xxh burst mode type 00 = not supported, 01 = supported 4bh 96h 0000h page mode type 00 = not supported, 01 = 4 word page 02 = 8 word page 4ch 98h 0000h acc(acceleration) supply minimum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 4dh 9ah 0085h acc(acceleration) supply maximum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 4eh 9ch 00c5h top/bottom boot block flag 02h = bottom boot device, 03h = top boot device 4fh 9eh 000xh
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 23 - preliminary device status flags flash memory has means to indicate its status of operation in the bank where a program or erase operation is in processes. addre ss must include bank address being excuted internal routine operation. the status is indicated by raising the device status flag vi a cor- responding dq balls or the ry/ by ball. the corresponding dq balls are dq7, dq6, dq5, dq3 and dq2. the status is as follows : table 13. hardware sequence flags notes: 1. dq2 will toggle when the device performs successive read operations from the erase suspended block. 2. if dq5 is high (exceeded timing limits), successive reads from a problem block will cause dq2 to toggle. status dq7 dq6 dq5 dq3 dq2 ry/ by in progress programming dq7 toggle 0 0 1 0 block erase or chip erase 0 toggle 0 1 toggle 0 erase suspend read erase suspended block 1 1 0 0 toggle (note 1) 1 erase suspend read non-erase sus- pended block data data data data data 1 erase suspend program non-erase sus- pended block dq7 toggle 0 0 1 0 exceeded time limits programming dq7 toggle 1 0 no toggle 0 block erase or chip erase 0 toggle 1 1 (note 2) 0 erase suspend program dq7 toggle 1 0 no toggle 0 dq7 : data polling when an attempt to read the device is made while executing the internal program, the complement of the data is written to dq7 as an indication of the routine in progress. when the routine is completed an attempt to access to the device will produce the true data written to dq7. when a user attempts to read the device during the erase operation, dq7 will be low. if the device is placed in the erase suspend mode, the status can be detected via the dq7 ball. if the system tries to read an address which belongs to a block that is being erased, dq7 will be high. if a non-erased block address is read, the device will produce the true data to dq7. if an attempt is made to program a protected block, dq7 outputs complements the data for approximately 1 m s and the device then returns to the read mode without changing data in the block. if an attempt is made to erase a protected block, dq7 outputs complement data in approximately 100us and the device then returns to the read mode without erasing the data in the block. dq6 : toggle bit toggle bit is another option to detect whether an internal routine is in progress or completed. once the device is at a busy sta te, dq6 will toggle. toggling dq6 will stop after the device completes its internal routine. if the device is in the erase suspend m ode, an attempt to read an address that belongs to a block that is being erased will produce a high output of dq6. if an address belo ngs to a block that is not being erased, toggling is halted and valid data is produced at dq6. if an attempt is made to program a protected block, dq6 toggles for approximately 1us and the device then returns to the read mo de without changing the data in the block. if an attempt is made to erase a protected block, dq6 toggles for approximately 100 m s and the device then returns to the read mode without erasing the data in the block. dq5 : exceed timing limits if the internal program/erase routine extends beyond the timing limits, dq5 will go high, indicating program/erase failure.
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 24 - preliminary ry/ by : ready/ busy flash memory has a ready / busy output that indicates either the completion of an operation or the status of internal algorithms. if the output is low, the device is busy with either a program or an erase operation. if the output is high, the device is ready to accept any read/write or erase operation. when the ry/ by ball is low, the device will not accept any additional program or erase commands with the exception of the erase suspend command. if flash memory is placed in an erase suspend mode, the ry/ by output will be high. for programming, the ry/ by is valid (ry/ by = 0) after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase, ry/ by is also valid after the rising edge of we pulse in the six write pulse sequence. for block erase, ry/ by is also valid after the rising edge of the sixth we pulse. the ball is an open drain output, allowing two or more ready/ busy outputs to be or-tied. an appropriate pull-up resistor is required for proper operation. rp = vcc f ready / busy open drain output device vss vcc f (max.) - v ol (max.) i ol + s i l = 2.9v 2.1ma + s i l where s i l is the sum of the input currents of all devices tied to the ready / busy ball. dq3 : block erase timer the status of the multi-block erase operation can be detected via the dq3 ball. dq3 will go high if 50 m s of the block erase time win- dow expires. in this case, the internal erase routine will initiate the erase operation.therefore, the device will not accept fu rther write commands until the erase operation is completed. dq3 is low if the block erase time window is not expired. within the block eras e time window, an additional block erase command (30h) can be accepted. to confirm that the block erase command has been accepted, the software may check the status of dq3 following each block erase command. dq2 : toggle bit 2 the device generates a toggling pulse in dq2 only if an internal erase routine or an erase suspend is in progress. when the devi ce executes the internal erase routine, dq2 toggles only if an erasing block is read. although the internal erase routine is in the exceeded time limits, dq2 toggles only if an erasing block in the exceeded time limits is read. when the device is in the erase suspend mode, dq2 toggles only if an address in the erasing block is read. if a non-erasing block address is read during the era se suspend mode, then dq2 will produce valid data. dq2 will go high if the user tries to program a non-erase suspend block while th e device is in the erase suspend mode. combination of the status in dq6 and dq2 can be used to distinguish the erase operation from the program operation. rp
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 25 - preliminary start dq7 = data ? no dq5 = 1 ? fail pass start dq6 = toggle ? no dq5 = 1 ? dq6 = toggle ? fail pass no no yes yes yes yes figure 12. temporary block group unprotect routine start reset =v id notes: 1. all protected block group s are unprotected. ( if wp /acc = v il , the two outermost boot blocks remain protected ) 2. all previously protected block groups are protected once again. (note 1) perform erase or program operations temporary block unprotect completed (note 2) reset =v ih figure 10. data polling algorithms figure 11. toggle bit algorithms dq7 = data ? no yes no yes
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 26 - preliminary recommended operating conditions (voltage reference to vss) parameter symbol min typ. max unit supply voltage vcc f , vcc s 2.7 3.0 3.3 v supply voltage vss 0 0 0 v absolute maximum ratings notes: 1. minimum dc voltage is -0.3v on input/ output balls. during transitions, this level may fall to -2.0v for periods <20ns. maxim um dc voltage on input / output balls is vcc+0.3v(max. 3.6v) which, during transitions, may overshoot to vcc+2.0v for periods <20ns. 2. minimum dc voltage is -0.3v on reset and wp /acc balls. during transitions, this level may fall to -2.0v for periods <20ns. maximum dc voltage on reset and wp /acc balls are 12.5v which, during transitions, may overshoot to 14.0v for periods <20ns. 3. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended period s may affect reliability. parameter symbol rating unit voltage on any ball relative to vss vcc vcc f , vcc s -0.3 to +3.6 v reset v in -0.3 to +12.5 wp /acc -0.3 to +12.5 all other balls -0.3 to vcc+0.3v(max.3.6v) temperature under bias t bias -40 to +125 c storage temperature t stg -65 to +150 c operating temperature t a -40 to +85 c dc characteristics parameter symbol test conditions min typ max unit common input leakage current i li v in =vss to vcc, vcc=vcc max -1.0 - +1.0 m a output leakage current i lo v out =vss to vcc, vcc=vcc max, oe =v ih -1.0 - +1.0 m a input low level v il -0.3 - 0.5 v input high level v ih 2.2 - vcc +0.3 v output low level v ol i ol = 2.1ma, vcc = vcc min - - 0.4 v output high level v oh i oh = -1.0ma, vcc = vcc min 2.3 - - v flash reset input leakage current i lit vcc f =vcc max, reset =12.5v - - 35 m a wp/ acc input leakage current i liw vcc f =vcc max, wp/ acc=12.5v - - 35 m a active read current (1) i cc 1 ce f =v il , oe =v ih 5mhz - 14 20 ma 1mhz - 3 6 active write current (2) i cc 2 ce f =v il , oe =v ih - 15 30 ma read while program current (3) i cc 3 ce f =v il , oe =v ih - 25 50 ma read while erase current (3) i cc 4 ce f =v il , oe =v ih - 25 50 ma program while erase suspend current i cc 5 ce f =v il , oe =v ih - 15 35 ma acc accelerated program current i acc ce f =v il , oe =v ih acc ball - 5 10 ma vcc f ball - 15 30 standby current i sb 1 vcc f =vcc f max, ce f =vcc f 0.3v, reset =vcc f 0.3v, wp /acc=vcc f 0.3v or vss 0.3v - 5 18 m a standby curren during reset i sb 2 vcc f =vcc f max , reset =vss 0.3v, wp /acc=vcc f 0.3v or vss 0.3v - 5 18 m a
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 27 - preliminary dc characteristics (continued) notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component(at 5 mhz). the read current is typically 14 ma (@ vcc f =3.0v , oe at v ih .) 2. i cc active during internal routine(program or erase) is in progress. 3. i cc active during read while write is in progress. 4. the high voltage ( v hh or v id ) must be used in the range of vcc f = 3.0v 0.3v 5. not 100% tested. 6. typical values are measured at vcc f = vcc s = 3.0v, ta=25 c , not 100% tested. parameter symbol test conditions min typ max unit flash automatic sleep mode i sb 3 v ih =vcc f 0.3v, v il =v ss 0.3v, oe =v il, i ol =i oh =0 - 5 18 m a voltage for wp /acc block temporarily unprotect and program acceleration (4) v hh vcc f = 3.0v 0.3v 8.5 - 12.5 v voltage for autoselect and block protect (4) v id vcc f = 3.0v 0.3v 8.5 - 12.5 v low vcc f lock-out voltage (5) v lko 1.8 - 2.5 v sram operating current i cc 1 cycle time=1 m s, 100% duty, cs 1 s 0.2v, cs2 s 3 vcc s -0.2v, lb 0.2v and/or ub 0.2v all outputs open, v in 0.2v or v in 3 vcc s -0.2v, byte s =vcc s 0.3v or vss 0.3v - - 3 ma i cc 2 cycle time=min, 100% duty, cs 1 s =v il , cs2 s =v ih , lb = v il and/or ub = v il , all outputs open, v in =v il or v ih, byte s =vcc s 0.3v or vss 0.3v - 22 28 ma standby current i sb cs 1 s 3 vcc s -0.2v, cs2 s 3 vcc s -0.2v ( cs 1 s controlled) or cs2 s 0.2v (cs2 s controlled), byte s =vcc s 0.3v or vss 0.3v, other input =0~vcc s - 0.5 15 m a ac test condition parameter value input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 output load c l = 30pf capacitance (t a = 25 c, vcc f = vcc s = 3.3v, f = 1.0mhz) note: capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 18 pf output capacitance c out v out =0v - 20 pf control ball capacitance c in2 v in =0v - 18 pf 0v vcc vcc/2 vcc/2 input pulse and test point input & output test point output load * cl= 30pf including scope c l device and jig capacitance
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 28 - preliminary alternate we controlled write notes: 1. not 100% tested. 2. the duration of the program or erase operation varies and is calculated in the internal algorithms. parameter symbol 70ns 80ns unit min max min max write cycle time (1) t wc 70 - 80 - ns address setup time t as 0 - 0 - ns t aso 55 - 55 - ns address hold time t ah 45 - 45 - ns t aht 0 - 0 - ns data setup time t ds 35 - 35 - ns data hold time t dh 0 - 0 - ns output enable setup time (1) t oes 0 - 0 - ns output enable hold time read (1) t oeh1 0 - 0 - ns toggle and data polling (1) t oeh2 10 - 10 - ns ce f setup time t cs 0 - 0 - ns ce f hold time t ch 0 - 0 - ns write pulse width t wp 35 - 35 - ns write pulse width high t wph 25 - 25 - ns programming operation word t pgm 14(typ.) 14(typ.) m s byte 9(typ.) 9(typ.) m s accelerated programming operation word t accpgm 9(typ.) 9(typ.) m s byte 7(typ.) 7(typ.) m s block erase operation (2) t bers 0.7(typ.) 0.7(typ.) sec vcc f set up time t vcs 50 - 50 - m s write recovery time from ry/ by t rb 0 - 0 - ns reset high time before read t rh 50 - 50 - ns reset to power down time t rpd 20 - 20 - m s program/erase valid to ry/ by delay t busy 90 - 90 - ns v id rising and falling time t vid 500 - 500 - ns reset pulse width t rp 500 - 500 - ns reset low to ry/ by high t rrb - 20 - 20 m s reset setup time for temporary unprotect t rsp 1 - 1 - m s reset low setup time t rsts 500 - 500 - ns reset high to address valid t rstw 200 - 200 - ns read recovery time before write t ghwl 0 - 0 - ns ce high during toggling bit polling t ceph 20 - 20 - ns oe high during toggling bit polling t oeph 20 - 20 - ns write(erase/program)operations flash ac characteristics
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 29 - preliminary flash ac characteristics write(erase/program)operations alternate ce f controlled writes notes: 1. not 100% tested. 2.this does not include the preprogramming time. parameter symbol 70ns 80ns unit min max min max write cycle time (1) t wc 70 - 80 - ns address setup time t as 0 - 0 - ns address hold time t ah 45 - 45 - ns data setup time t ds 35 - 35 - ns data hold time t dh 0 - 0 - ns output enable setup time (1) t oes 0 - 0 - ns output enable hold time read (1) t oeh1 0 - 0 - ns toggle and data polling (1) t oeh2 10 - 10 - ns we setup time t ws 0 - 0 - ns we hold time t wh 0 - 0 - ns ce f pulse width t cp 35 - 35 - ns ce f pulse width high t cph 25 - 25 - ns programming operation word t pgm 14(typ.) 14(typ.) m s byte 9(typ.) 9(typ.) m s accelerated programming operation word t accpgm 9(typ.) 9(typ.) m s byte 7(typ.) 7(typ.) m s block erase operation (2) t bers 0.7(typ.) 0.7(typ.) sec byte switching low to output high-z t flqz 25 - 25 - ns erase and program performance notes: 1. 25 c, vcc f = 3.0v 100,000 cycles, typical pattern . 2. system-level overhead is defined as the time required to execute the four bus cycle command necessary to program each byte. in the preprogramming step of the internal erase routine, all bytes are programmed to 00h before erasure. parameter limits unit comments min typ max block erase time - 0.7 15 sec excludes 00h programming prior to erasure chip erase time - 49 - sec word programming time - 14 330 m s excludes system-level overhead byte programming time - 9 210 m s excludes system-level overhead accelerated byte/word program time word mode - 9 210 m s excludes system-level overhead byte mode - 7 150 m s excludes system-level overhead chip programming time word mode - 28 84 sec excludes system-level overhead byte mode - 36 108 sec erase/program endurance 100,000 - - cycles minimum 100,000 cycles guaran- teed
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 30 - preliminary read operations flash switching waveforms oe address t ce t oeh1 ce f outputs we high-z output valid t rc address stable t aa t oe t oh high-z t df ry/ by high note: 1. not 100% tested. parameter symbol 70ns 80ns unit min max min max read cycle time t rc 70 - 80 - ns address access time t aa - 70 - 80 ns chip enable access time t ce - 70 - 80 ns output enable time t oe - 25 - 25 ns ce f & oe disable time (1) t df - 16 - 16 ns output hold time from address, ce f or oe t oh 0 - 0 - ns oe hold time t oeh1 0 - 0 - ns
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 31 - preliminary hardware reset/read operations flash switching waveforms parameter symbol 70ns 80ns unit min max min max read cycle time t rc 70 - 80 - ns address access time t aa - 70 - 80 ns chip enable access time t ce - 70 - 80 ns output hold time from address, ce f or oe t oh 0 - 0 - ns reset pulse width t rp 500 - 500 - ns reset high time before read t rh 50 - 50 - ns reset address ce f outputs high-z t rc address stable t aa t ce t oh t rh t rh t rp output valid
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 32 - preliminary alternate we controlled program operations flash switching waveforms notes: 1. dq7 is the output of the complement of the data written to the device. 2. dout is the output of the data written to the device. 3. pa : program address, pd : program data 4. the illustration shows the last two cycles of the program command sequence. oe address t cs ce f data we t ah t oh t df t as t rc t oe t ce t ds t dh t wp t oes t pgm status dout 555h pa pa a0h data polling t ch pd t wph ry/ by t busy t rb t wc parameter symbol 70ns 80ns unit min max min max write cycle time t wc 70 - 80 - ns address setup time t as 0 - 0 - ns address hold time t ah 45 - 45 - ns data setup time t ds 35 - 35 - ns data hold time t dh 0 - 0 - ns ce f setup time t cs 0 - 0 - ns ce f hold time t ch 0 - 0 - ns oe setup time t oes 0 - 0 - ns write pulse width t wp 35 - 35 - ns write pulse width high t wph 25 - 25 - ns programming operation word t pgm 14(typ.) 14(typ.) us byte 9(typ.) 9(typ.) us accelerated programming operation word t accpgm 9(typ.) 9(typ.) m s byte 7(typ.) 7(typ.) m s read cycle time t rc 70 - 80 - ns chip enable access time t ce - 70 - 80 ns output enable time t oe - 25 - 25 ns ce f & oe disable time t df - 16 - 16 ns output hold time from address, ce f or oe t oh 0 - 0 - ns program/erase valide to ry/ by delay t busy 90 - 90 - ns recovery time from ry/ by t rb 0 - 0 - ns
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 33 - preliminary alternate ce f controlled program operations flash switching waveforms notes: 1. dq7 is the output of the complement of the data written to the device. 2. dout is the output of the data written to the device. 3. pa : program address, pd : program data 4. the illustration shows the last two cycles of the program command sequence. oe address we data ce f t ah t as t ds t dh t cp t oes a0h 555h pa pa status dout data polling t cph t ws t pgm ry/ by t busy t rb pd t wc parameter symbol 70ns 80ns unit min max min max write cycle time t wc 70 - 80 - ns address setup time t as 0 - 0 - ns address hold time t ah 45 - 45 - ns data setup time t ds 35 - 35 - ns data hold time t dh 0 - 0 - ns oe setup time t oes 0 - 0 - ns we setup time t ws 0 - 0 - ns we hold time t wh 0 - 0 - ns ce f pulse width t cp 35 - 35 - ns ce f pulse width high t cph 25 - 25 - ns programming operation word t pgm 14(typ.) 14(typ.) m s byte 9(typ.) 9(typ.) m s accelerated programming operation word t accpgm 9(typ.) 9(typ.) m s byte 7(typ.) 7(typ.) m s program/erase valide to ry/ by delay t busy 90 - 90 - ns recovery time from ry/ by t rb 0 - 0 - ns
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 34 - preliminary flash switching waveforms parameter symbol 70ns 80ns unit min max min max chip enable access time t ce - 70 - 80 ns ce f to byte switching low or high t elfl /t elfh - 5 - 5 ns byte switching low to output high-z t flqz - 25 - 25 ns byte switching high to output active t fhqv - 25 - 25 ns oe t flqz ce f dq0-dq7 byte we byte timing diagram for write operation the falling edge of the last we signal ce f byte t hold (t ah ) dq15/a-1 t elfl address input (a-1) t set (t as ) word to byte timing diagram for read operation byte to word timing diagram for read operation data output (dq0-dq7) dq8-dq14 data output (dq8-dq14) data output (dq15) oe t fhqv ce f dq0-dq7 byte dq15/a-1 t elfh data output dq8-dq14 address input (a-1) data output (dq8-dq14) (dq15) t ce t ce data output (dq0-dq7)
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 35 - preliminary flash switching waveforms chip/block erase operations parameter symbol 70ns 80ns unit min max min max write cycle time t wc 70 - 80 - ns address setup time t as 0 - 0 - ns address hold time t ah 45 - 45 - ns data setup time t ds 35 - 35 - ns data hold time t dh 0 - 0 - ns oe setup time t oes 0 - 0 - ns ce f setup time t cs 0 - 0 - ns write pulse width t wp 35 - 35 - ns write pulse width high t wph 25 - 25 - ns read cycle time t rc 70 - 80 - ns vcc f set up time t vcs 50 - 50 - m s oe address t cs ce f data we t ah t as t rc t ds t dh 80h aah aah 55h 30h 10h for chip erase 555h 2aah 555h 555h 2aah ba 555h for chip erase t wph t wp t oes 55h ry/ by t wc t vcs vcc f note: ba : block address
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 36 - preliminary read while write operations flash switching waveforms parameter symbol 70ns 80ns unit min max min max write cycle time t wc 70 - 80 - ns write pulse width t wp 35 - 35 - ns write pulse width high t wph 25 - 25 - ns address setup time t as 0 - 0 - ns address hold time t ah 45 - 45 - ns data setup time t ds 35 - 35 - ns data hold time t dh 0 - 0 - ns read cycle time t rc 70 - 80 - ns chip enable access time t ce - 70 - 80 ns address access time t aa - 70 - 80 ns output enable access time t oe - 25 - 25 ns oe setup time t oes 0 - 0 - ns oe hold time t oeh2 10 - 10 - ns ce f & oe disable time t df - 16 - 16 ns address hold time t aht 0 - 0 - ns ce f high during toggle bit polling t ceph 20 - 20 - ns note: this is an example in the program-case of the read while write function. d a1 : address of bank1, da2 : address of bank 2 pa = program address at one bank , ra = read address at the other bank , pd = program data in , rd = read data out oe ce f dq we t rc read command command read read read t ah t aa t ce t as t aht t as t ceph t oe t oes t wp t oeh2 t df t ds t dh t df da1 da2 da1 da1 da2 da2 (555h) (pa) (pa) valid output valid output valid in put valid output valid in put status address (a0h) (pd) t rc t rc t rc t wc t wc
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 37 - preliminary data polling during internal routine operation flash switching waveforms parameter symbol 70ns 80ns unit min max min max program/erase valid to ry/ by delay t busy 90 - 90 - ns chip enable access time t ce - 70 - 80 ns output enable time t oe - 25 - 25 ns ce f & oe disable time t df - 16 - 16 ns output hold time from address, ce f or oe t oh 0 - 0 - ns oe hold time t oeh2 10 - 10 - ns oe t ce t oeh2 ce f dq7 we t oe high-z t df note: *dq7=vaild data (the device has completed the internal operation). dq7 *dq7 = valid data t oh t pgm or t bers high-z valid data dq0-dq6 data in data in we ry/ by timing diagram during program/erase operation the rising edge of the last we signal ce f ry/ by t busy entire progrming or erase operation status data
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 38 - preliminary toggle bit during internal routine operation flash switching waveforms t dh ce f address* oe dq6/dq2 we ry/ by data in t aht t aht t aso t as t ceph t oeh2 t oeph status data t o e status data status data array data out note: address for the write operation must include a bank address (a19~a20) where the data is written. dq 6 we dq 2 enter embedded erasing erase suspend enter erase suspend program erase suspend program erase resume erase erase suspend read erase erase complete erase suspend read note: dq2 is read from the erase-suspended block. toggle dq 2 and dq 6 with oe or ce f parameter symbol 70ns 80ns unit min max min max output enable access time t oe - 25 - 25 ns oe hold time t oeh2 10 - 10 - ns address hold time t aht 0 - 0 - ns address setup t aso 55 - 55 - ns address setup time t as 0 - 0 - ns data hold time t dh 0 - 0 - ns ce f high during toggle bit polling t ceph 20 - 20 - ns oe high during toggle bit polling t oeph 20 - 20 - ns
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 39 - preliminary reset timing diagram flash switching waveforms parameter symbol 70ns 80ns unit min max min max reset pulse width t rp 500 - 500 - ns reset low to valid data (during internal routine) t ready - 20 - 20 m s reset low to valid data (not during internal routine) t ready - 500 - 500 ns reset high time before read t rh 50 - 50 - ns ry/ by recovery time t rb 0 - 0 - ns reset high to address valid t rstw 200 - 200 - ns reset low set-up time t rsts 500 - 500 - ns reset t rp power-up and reset timing diagram ce f or oe ry/ by t ready t rb reset ce f or oe ry/ by t rh t ready t rp reset timings not during internal routine reset timings during internal routine high reset t aa vcc f address data t rsts
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 40 - preliminary block group protect & unprotect operations flash switching waveforms ce f temporary block group unprotect program or erase command sequence reset we t rsp ry/ by t vid v id vss,v il , or v ih vss,v il , or v ih t rrb t vid bga,a6 a1,a0 reset ce f we d ata oe vss,v il , 60h 60h 40h status* block group protect / unprotect verify 1 m s block group protect:150 m s block group unprotect:15ms notes: block group protect (a6= v il , a1= v ih , a0= v il ) , status=01h block group unprotect (a6= v ih , a1= v ih , a0= v il ) , status=00h bga = block group address (a12 ~ a20) ry/ by v id valid valid valid t busy t rb or v ih vss,v il , or v ih
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 41 - preliminary sram data retention characteristics 1. cs 1 s 3 vcc s -0.2v, cs2 s 3 vcc s -0.2v( cs 1 s controlled) or cs2 s 0.2v(cs2 s controlled) 2. typical values are measured at vcc=3.0v, ta=25 c , not 100% tested. item symbol test condition min typ max unit vcc s for data retention v dr cs 1 s 3 vcc s -0.2v 1.5 - 3.3 v data retention current i dr vcc s =3.0v, cs 1 s 3 vcc s -0.2v - 0.5 15 m a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr trc - - sram ac characteristics parameter list symbol 55ns units min max read read cycle time t rc 55 - ns address access time t aa - 55 ns chip select to output t co1 , t co2 - 55 ns output enable to valid output t oe - 25 ns ub , lb access time t ba - 55 ns chip select to low-z output t lz1 , t lz2 10 - ns ub , lb enable to low-z output t blz 10 - ns output enable to low-z output t olz 5 - ns chip disable to high-z output t hz1 , t hz2 0 20 ns ub , lb disable to high-z output t bhz 0 20 ns output disable to high-z output t ohz 0 20 ns output hold from address change t oh 10 - ns write write cycle time t wc 55 - ns chip select to end of write t cw 45 - ns address set-up time t as 0 - ns address valid to end of write t aw 45 - ns ub , lb valid to end of write t bw 45 - ns write pulse width t wp 40 - ns write recovery time t wr 0 - ns write to output high-z t whz 0 20 ns data to write time overlap t dw 20 - ns data hold from write time t dh 0 - ns end write to output low-z t ow 5 - ns
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 42 - preliminary sram timing diagrams address data out previous data valid data valid timing waveform of read cycle(1) (address controlled , cs 1 s = oe =v il , cs2 s = we =v ih , ub or/and lb =v il ) timing waveform of read cycle(2) ( we =v ih ) data valid high-z t rc cs 1 s address ub , lb oe data out t aa t rc t oh t oh t aa t co1 t ba t oe t olz t blz t lz t ohz t bhz t hz notes (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. cs2 s t co2
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 43 - preliminary sram timing diagrams timing waveform of write cycle(1) ( we controlled) address cs 1 s data undefined ub , lb we data in data out timing waveform of write cycle(2) ( cs 1 s controlled) address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t wr(4) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) high-z high-z data valid t as(3) cs 2 s cs 1 s cs 2 s t cw(2)
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 44 - preliminary address data valid ub , lb we data in data out high-z high-z timing waveform of write cycle(3) ( ub , lb controlled) notes (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs 1 s and low we . a write begins when cs 1 s goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest tran- sition when cs 1 s goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs 1 s going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs 1 s or we going high. t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw sram data retention wave form cs 1 s controlled v cc s 2.7v 2.2v v dr cs 1 s vss data retention mode cs 1 s 3 vcc s - 0.2v t sdr t rdr t as(3) cs 1 s cs 2 s cs 2 s controlled v cc s 2.7v 0.4v v dr cs 2 s vss data retention mode t sdr t rdr cs 2 s 0.2v t cw(2)
mcp memory k5a3x80yt(b)c revision 0.0 november 2002 - 45 - preliminary package dimension 69-ball tape ball grid array package (measured in millimeters) top view bottom view side view 0.45 0.05 0.08max 0 . 3 2 0 . 0 5 1 . 1 0 0 . 1 0 #a1 1 4 2 7 6 5 3 8 a b c e g d f h 0.80 x9=7.20 a 0 . 8 0 x 9 = 7 . 2 0 1 1 . 0 0 0 . 1 0 3.60 69- ? 0.45 0.05 9 10 j k 3 . 6 0 0 . 8 0 b 8.00 0.10 0.20 m a b ? (datum a) (datum b) 1 1 . 0 0 0 . 1 0 8.00 0.10 11.00 0.10 0.80

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